Gain enhancement for cascode structure

ABSTRACT

Aspects of the present invention provide apparatuses and methods to provide significant gain enhancement for a cascode structure for a differential amplifier. The cascode structure of the differential amplifier can include first and second pairs of output transistors. The second pair of output transistors can be configured to approximately cancel modulation effects of the first pair of output transistors induced by changes in a differential output of differential amplifier, thereby resulting in conditions for providing enhanced gain.

RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.13/289,662 filed Nov. 4, 2011, the disclosure of which is incorporatedherein by this reference.

BACKGROUND

1. Field of the Invention

The present invention generally relates to amplifiers. Morespecifically, the present invention provides significant gainenhancement while minimizing noise introduction for differentialamplifiers using cascode structures.

2. Background Art

Differential amplifiers are designed generally to amplify input signalswhile minimizing noise introduction and signal distortion. Conventionaldifferential amplifiers are designed often using larger-sizedtransistors to boost gain and lower noise but at the expense ofintroducing higher levels of parasitic capacitance. Alternatively,conventional differential amplifiers can use smaller-sized transistorsthat provide less gain to maintain signal integrity. However, to providerequired gain levels, conventional differential amplifiers that usesmaller-sized transistors often require multiple gain stages andtherefore additional circuit elements which increases design complexityand costs.

FIG. 1 illustrates a conventional differential amplifier with a cascodestage 100. The conventional differential amplifier 100 includesdifferential transistor pair 102 and 104 and cascode transistor pair 106and 108. Transistor 102 is coupled to a first component of adifferential input 110. The first component of differential input 110receives a first component of a differential input signal (labeled as“IN-i” in FIG. 1). The first component of the differential input signalcan be, for example, a first component of a differential input voltage.Transistor 104 is coupled to a second component of a differential input112. The second component of differential input 112 receives a secondcomponent of a differential input signal (labeled as “IN-n” in FIG. 1).The second component of the differential input signal can be, forexample, a second component of a differential input voltage. As furthershown in FIG. 1, the differential transistor pair 102 and 104 is coupledto a bias current source 114.

The cascade transistor pair 106 and 108 is coupled to the differentialtransistor pair 102 and 104 to increase the gain of the conventionaldifferential amplifier 100. Transistor 106 is coupled to a biasingsource (labeled for simplicity as “BIAS” in FIG. 1). The biasing sourcecan be, for example, a bias voltage supply. Transistor 106 is coupled toa first component of a differential output 116. The first component ofdifferential output 116 provides a first component of a differentialoutput signal (labeled as “OUT-n” in FIG. 1). The first component of thedifferential output signal can be, for example, a first component of adifferential output voltage. Transistor 108 is also coupled to a biasingsource (labeled for simplicity as “BIAS” in FIG. 1). The biasing sourcecan be, for example, a bias voltage supply. Transistor 108 is coupled toa second component of a differential output 118. The second component ofdifferential output 118 provides a second component of a differentialoutput signal (labeled for simplicity as “OUT-i” in FIG. 1). The secondcomponent of the differential output signal can be, for example, asecond component of a differential output voltage.

The conventional differential amplifier 100 is coupled to a second stageamplifier (not shown in FIG. 1). The goal of the conventionaldifferential amplifier 100 is to amplify a differential input 110, 112to provide an amplified differential output 116, 118 while minimizingthe amount of noise and signal distortion introduced duringamplification. Larger-sized transistors generally provide higher gainbut at the expense of introducing more noise into the amplified signal.Smaller-sized transistors generally introduce less relative noise but atthe expense of lower gain.

As the size of a CMOS transistor is decreased, the intrinsic gain of theCMOS transistor—defined as the change in drain voltage for a change ingate voltage (or source voltage)—also decreases. The intrinsic gain cangenerally be considered to be the ratio of R_(DS) to 1/g_(m) of the CMOStransistor, where R_(DS) is the drain-to-source resistance and g_(m) isthe transconductance of the CMOS transistor.

For a CMOS transistor fabricated in a 65 nm process, the intrinsic gainof the CMOS transistor is approximately 5 to 7. Using CMOS transistorsof this scale in the conventional differential amplifier 100, the gainof the differential transistor pair 102, 104 is approximately 5 to 7,the gain of the cascade transistor pair 106, 108 is also approximately 5to 7, and the overall gain of the conventional differential amplifier isapproximately 25 to 49. While CMOS transistors at the 65 nm nodegenerally provide greater bandwidth, the overall gain of theconventional differential amplifier 100 is generally too low for manyapplications when such transistors are used. Using larger-sized CMOStransistors to boost the overall gain of the conventional differentialamplifier 100, however, introduces too much parasitic capacitance formany applications. The design of the conventional differential amplifier100 may therefore be deficient in terms of overall gain when, forexample, CMOS transistors fabricated in a 65 nm process, or even largertransistors, are employed.

Accordingly, what is needed is a differential amplifier design that canprovide high levels of gain using low noise transistors withoutrequiring multiple gain stages.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate the present invention and, togetherwith the description, further serve to explain the principles of theinvention and to enable one skilled in the pertinent art to make and usethe invention.

FIG. 1 illustrates a conventional differential amplifier with a cascodestage.

FIG. 2 illustrates a differential amplifier according to an aspect ofthe present invention.

FIG. 3 illustrates a differential amplifier with multiple inputtransistors according to an aspect of the present invention.

FIG. 4 illustrates a differential amplifier with switched capacitorsaccording to an aspect of the present invention.

FIG. 5 provides a flowchart illustrating a method for providing enhancedgain according to an aspect of the present invention.

DETAILED DESCRIPTION

Aspects of the present invention provide apparatuses and methods toprovide significant gain enhancement for a cascode structure for adifferential amplifier. The cascode structure of the differentialamplifier can include first and second pairs of output transistors. Thesecond pair of output transistors can be configured to approximatelycancel modulation effects of the first pair of output transistors,thereby resulting in conditions for providing enhanced gain.

First outputs of the first pair of output transistors can provide adifferential output of the differential amplifier. Second outputs of thefirst pair of transistors can be coupled to input transistors thatreceive a differential input signal. Inputs of the second pair of outputtransistors can be cross-coupled to the first outputs of the first pairof output transistors. First outputs of the second pair of outputtransistors can be coupled to the first outputs of the first pair ofoutput transistors. The second pair of output transistors can be sizedto be proportionally larger than the first pair of output transistorsrelative to the intrinsic gains of the first pair of output transistors.In doing so, second outputs of the second pair of output transistors canprovide changes in output to approximately match changes in output ofthe second outputs of the first pair of output transistors when changesin the differential output occur. The modulation effects of the secondoutputs of the first pair of output transistors are therebyapproximately canceled by the output provided by the second outputs ofthe second pair of output transistors. As a result, an approximatelynon-zero change in the differential output of the differential amplifiercan be provided for approximately no change in the combined secondoutputs of the first and second pairs of output transistors.

FIG. 2 illustrates a differential amplifier 200 according to an aspectof the present invention. The differential amplifier 200 provides acascoded arrangement of transistors that provides significant gainenhancement over the cascoded arrangement of the conventionaldifferential amplifier 100 of FIG. 1.

The differential amplifier 200 can include a differential transistorpair 202-1 and 202-2 and cascode transistor pairs 206-1/206-2 and208-1/208-2. Transistor 202-1 can be coupled to a first component of adifferential input 210-1. The first component of differential input210-1 can receive a first component of a differential input signal(labeled as “IN-i” in FIG. 2). The first component of the differentialinput signal can be, for example, a first component of a differentialinput voltage. Transistor 202-2 can be coupled to a second component ofa differential input 210-2. The second component of differential input210-2 can receive a second component of a differential input signal(labeled as “IN-n” in FIG. 2). The second component of the differentialinput signal can be, for example, a second component of a differentialinput voltage. The differential transistor pair 202-1 and 202-2 can becoupled to a bias current source 212. The differential transistor pair202-1 and 202-2 can be considered to be input transistors or an inputtransistor pair.

As further shown in FIG. 2, transistor 202-1 can be coupled to cascodetransistors 206-1 and 208-1. Specifically, the drain of transistor 202-1can be coupled to the sources of cascode transistors 206-1 and 208-1.Similarly, transistor 202-2 can be coupled to cascode transistors 206-2and 208-2. Specifically, the drain of transistor 202-2 can be coupled tothe sources of cascode transistors 206-2 and 208-2.

The transistor 206-1 can be provided in a diode configuration.Specifically, a gate of transistor 206-1 can be coupled to its drain.The gate of transistor 206-1 can also be coupled to a drain oftransistor 208-1 and can provide a first component of a differentialoutput 214-1. The first component of the differential output 214-1 canprovide a first component of a differential output signal (labeled as“OUT-n” in FIG. 2). The first component of the differential outputsignal can be, for example, a first component of a differential outputvoltage. Similarly, the transistor 206-2 can be provided in a diodeconfiguration. Specifically, a gate of transistor 206-2 can be coupledto its drain. The gate of transistor 206-2 can also be coupled to adrain of transistor 208-2 and can provide a second component of adifferential output 214-2. The second component of the differentialoutput 214-2 can provide a second component of a differential outputsignal (labeled as “OUT-i” in FIG. 2). The second component of thedifferential output signal can be, for example, a second component of adifferential output voltage. The transistors 206-1 and 206-2 can beconsidered to be a pair of diode configured transistors coupled to thedifferential output of the differential amplifier 200 (differentialoutputs 214-1 and 214-2, respectively).

As further shown in FIG. 2, the transistor 208-1 can be cross-coupledwith the transistor pair 206-2/208-2. Specifically, the gate of thetransistor 208-1 can be coupled to the drains of the transistor pair206-2 and 208-2 and to the second component of the differential output214-2. Likewise, the transistor 208-2 can be cross-coupled with thetransistor pair 206-1/208-1. Specifically, the gate of the transistor208-2 can be coupled to the drains of the transistor pair 206-1 and208-1 and to the first component of the differential output 214-1. Thetransistors 208-1 and 208-2 can be considered to be cross-coupledtransistors or a cross-coupled transistor pair.

The differential amplifier 200 can be configured to provide enhancedgain in comparison to the conventional differential amplifier 100depicted in FIG. 1. The differential amplifier 200 can be configured toprovide enhanced gain with the diode configured transistor pair 206-1and 206-2 and the cross-coupled transistor pair 208-1 and 208-2 whenimplemented with larger-sized transistors to ensure the introduction ofrelatively low unwanted noise during amplification of differential inputsignals.

The ability of the differential amplifier 200 to provide enhancedgain—using the cascade structure formed by the transistors 206-1, 206-2,208-1 and 208-2—can be understood by example operation of thedifferential amplifier 200. Specifically, if a differential outputvoltage provided by the first differential output 214-1 changes by +1volt (V), then the differential output voltage provided by the seconddifferential output 214-2 corresponding will approximately change by −1V. With this change at the differential outputs 214-1 and 214-2, thesource of transistor 206-1 will be pulled to change by +1 V due to theconfiguration of the differential amplifier 200 (e.g., due to the diodefollower configuration of the transistor 206-1). Further, the source oftransistor 208-1 will be pulled to change by −1 V. The voltage change atthe sources of the transistors 206-1 and 208-1 are therefore in tensionand ideally can cancel each other out. When this occurs, the overallvoltage change at the sources of the transistors 206-1 and 208-1 can bezero for a non-zero voltage change at the drains of the transistors206-1 and 208-1. Recalling that the gain is defined to be the change indrain voltage for a change in source voltage, under such conditions thegain provided by the transistor pair 206-1 and 208-1 at the differentialoutput 214-1 can be infinite.

In practice, the finite drain-to-source resistances of the transistors206-1, 208-1 and 202-1 can challenge the ability of the transistor 208-1to provide a change in voltage at its source that exactly counteractsthe change in voltage at the source of the transistor 206-1. Therefore,the transistor 208-1 can be sized slightly larger than the transistors206-1 and 202-1 to account for the finite drain-to-source resistances ofthese transistors by providing the transistor 208-1 with a larger g_(m)as compared to the transistor 206-1. Specifically, the transistor 208-1can be sized to be proportionally larger relative to the intrinsic gainof the transistor 206-1. In doing so, the transistor 208-1 can provide avoltage change at its source that more closely offsets or cancels thevoltage change at the source at the transistor 206-1, thereby resultingin conditions providing enhanced gain. The transistors 206-1 and 202-1can be sized to be approximately the same.

As a rule of thumb (for example, for transistors fabricated by a 65 nmprocess), transistor 208-1 can be sized approximately 20% larger thanthe transistor 206-1 to provide near ideal conditions such that enhancedgain conditions are achieved—i.e., such that approximately no overallvoltage change occurs at the sources of the transistors 206-1 and 208-1for a non-zero voltage change at the drains of the transistors 206-1 and208-1. Infinite gain conditions can approximately occur when thefollowing condition is met:

R _(gm208-1) ≈R _(gm206-1) ∥R _(DS206-1) ∥D _(DS208-1)

where R_(gm208-1) is the transresistance of transistor 208-1,R_(gm206-1) is the transresistance of transistor 206-1, R_(DS206-1) isthe drain-to-source resistance of transistor 206-1, and R_(DS208-1) isthe drain-to-source resistance of transistor 208-1.

The diode follower configuration of the transistor 206-1, thecross-coupling of the transistor 208-1, and the increase of the sizingof the transistor 208-1 relative to the size of the transistor 206-1(and therefore intrinsic gain of the transistor 206-1), enables thedifferential amplifier 200—and in particular the transistor 208-1—tocancel the modulation effects at the source of the transistor 206-1 dueto the finite drain-to-source resistances of the constituenttransistors. By canceling the modulation of the source of the transistor206-1, the differential amplifier 200 can provide an approximatelyinfinite voltage gain with the cascode transistors 206-1 and 208-1 (byhaving a differential voltage change of approximately zero at thesources of transistors 206-1 and 208-1 for a non-zero differentialvoltage change at the first differential output 214-1 as discussedabove).

The operation and relative sizing of the transistors 206-2 and 208-2 canmimic the operation of the transistors 206-1 and 208-1 as describedabove with similar results and benefits. In short, the diode followerconfiguration of the transistor 206-2, the cross-coupling of thetransistor 208-2, and the increase of the sizing of the transistor 208-2relative to the size of the transistor 206-2 (and therefore intrinsicgain of the transistor 206-2), enables the transistor 208-2 to cancelthe modulation effects at the source of the transistor 206-2 due to thefinite drain-to-source resistance of the constituent transistors. Aswith the transistors 206-1 and 208-1, by canceling the modulation of thesource of the transistor 206-2, the differential amplifier 200 can beable to provide an approximately infinite voltage gain with the cascodetransistors 206-2 and 208-2 (by having a differential voltage change ofapproximately zero at the sources of transistors 206-2 and 208-2 for anon-zero differential voltage change at the second differential output214-2 as discussed above).

The gain enhancement provided by the configuration of the differentialamplifier 200 can achieve very high increases in gain over the gainprovided by the conventional differential amplifier 100. The increasedgain provided by the differential amplifier 200 can be achieved usinglarger-sized transistors to limit the amount of unwanted noiseintroduced by the differential amplifier 200. The very high gain levelsprovided by the differential amplifier 200 can vary with process andtemperature.

The differential amplifier 200 can include additional biasing elementsnot shown to ensure proper operation of the transistors 202-1, 202-2,206-1, 206-2, 208-1 and 208-2 (for example, to ensure operation insaturation mode) and which are not shown in FIG. 2 for simplicity. Thedifferential amplifier 200 is also not limited to implementation usingNMOS transistors but can be implemented using PMOS technology as well asother transistor technologies including BJTs.

FIG. 3 illustrates a differential amplifier 300 according to an aspectof the present invention. The differential amplifier 300 also provides acascoded arrangement of transistors that also provides significant gainenhancement over the cascoded arrangement of the conventionaldifferential amplifier 100 of FIG. 1, in a manner and arrangementsimilar to the differential amplifier 200 of FIG. 2

In the differential amplifier 300, the input differential transistorspair 202-1 and 202-2 of the differential amplifier 200 can be brokeninto two transistors—specifically, transistor pair 302-1 and 304-1 andtransistor pair 302-2 and 304-2. The differential amplifier 300 caninclude cascade transistor pairs 306-1/308-1 and 306-2/308-2 coupled tothe input transistor pairs 302-1/304-1 and 302-2/304-2, respectively, asshown in FIG. 3. Input transistor pairs 302-1/304-1 and 302-2/304-2 canbe coupled to a bias current source 312.

Transistor pair 302-1/304-1 can be coupled to first differential input310-1 while transistor pair 302-2/304-2 can be coupled to seconddifferential input 310-2. As before, transistor 306-1 can be configuredin a diode follower configuration and transistor 308-1 can becross-coupled to second differential output 314-2. Transistor 306-2 canbe similarly configured in a diode follower configuration and transistor308-1 can be cross-coupled to first differential output 314-1.

In contrast to the differential amplifier 200, the transistor 302-1 canbe coupled to transistor 306-1 and the transistor 304-1 can be coupledto transistor 308-1. Further, the transistor 302-2 can be coupled totransistor 306-2 and the transistor 304-2 can be coupled to transistor308-2.

The ability of the differential amplifier 300 to provide enhancedgain—using cross-coupled transistors 308-1 and 308-2, diode followerconfigured transistors 306-1 and 306-2, and input differentialtransistor pairs 302-1/302-2 and 304-1/304-2—can be understood byexample operation of the differential amplifier 300. Specifically, if adifferential output voltage provided by the first differential output314-1 changes by +1 V, then the differential output voltage provided bythe second differential output 314-2 corresponding will approximatelychange by −1 V. With this change at the differential outputs 314-1 and314-2, the source of transistor 306-1 will be pulled to change by +1 Vdue to the configuration of the differential amplifier 300 (e.g., due tothe diode follower configuration of the transistor 306-1). Further, thesource of transistor 308-1 will be pulled to change by −1 V. Thedifferent voltage change at the sources of the transistors 306-1 and308-1 are therefore in tension and ideally can cancel each other out.Specifically, the net current change at the outputs of the sources of306-1 and 308-1 can be approximately zero. When this occurs, the overallcombined voltage change at the sources of the transistors 306-1 and308-1 can be zero for a non-zero voltage change at the drains of thetransistors 306-1 and 308-1, thereby enabling the differential amplifier300 to ideally provide infinite gain.

As with the differential amplifier 200, in practice, the finitedrain-to-source resistances of the component transistors can beaccounted for to ensure the differential amplifier 300 providessignificant gain enhancement. Specifically, the finite drain-to-sourceresistances of the transistors 302-1, 304-1, 306-1 and 308-1 canchallenge the ability of the transistor 308-1 to provide an outputsource current that that exactly counteracts the change in output sourcecurrent of the transistor 306-1. Therefore, the transistor 308-1 can besized slightly larger than the transistors 306-1, 302-1 and 304-1 toaccount for the finite drain-to-source resistance of these transistorsby providing the transistor 308-1 with a larger g_(m) as compared to thetransistor 306-1. Specifically, the transistor 308-1 can be sized to beproportionally larger relative to the intrinsic gain of the transistor306-1. In doing so, the transistor 308-1 can provide a voltage/currentchange at its source that more closely offsets or cancels thevoltage/current change at the source at the transistor 306-1, therebyresulting in conditions providing enhanced gain. The transistors 302-1,304-1, and 306-1 can be sized to be approximately the same.

The operation and relative sizing of the transistors 306-2 and 308-2 canmimic the operation of the transistors 306-1 and 308-1 as describedabove with similar results and benefits.

Infinite gain conditions can approximately occur when the followingcondition is met:

(1−K _(A))/(R _(gm306-1) ∥R _(DS306-1))≈[R _(DS304-1)(1−K _(B))−R_(DS308-1)(1+K _(B))/R _(DS304-1) ∥R _(DS308-1)]

K _(A)≈(R _(DS302-1) ∥R _(gm306-1) ∥R _(DS306-1))/(R _(gm306-1) ∥R_(DS306-1))

K _(B)≈(R _(DS304-1) ∥R _(gm304-2) ∥R _(DS208-1))/(R _(DS304-1) ∥R_(DS308-1))

where R_(gm306-1) is the transresistance of transistor 306-1,R_(DS306-1) is the drain-to-source resistance of transistor 306-1,R_(DS304-1) is the drain-to-source resistance of transistor 304-1,R_(DS308-1) is the drain-to-source resistance of transistor 308-1,R_(DS302-1) is the drain-to-source resistance of transistor 302-1, andR_(gm304-2) is the transresistance of transistor 304-2.

The diode configuration of the transistors 306-1 and 306-2, thecross-coupling of the transistors 308-1 and 308-2, and the increase ofthe sizing of the transistors 308-1 and 308-2 relative to the sizes ofthe other transistors (and therefore the intrinsic gain of the othertransistors), enables the differential amplifier 300—and in particularthe transistors 308-1 and 308-2—to cancel the modulation effects of theinput transistors (302-1/302-2 and 304-1/304-2) and the diode followerconfigured transistors (306-1 and 306-2) due to their finitedrain-to-source resistances. By canceling these modulation effects, thedifferential amplifier 300 can provide an approximately infinite voltagegain with the cascode transistor pairs 306-1/308-1 and 306-2/308-2 (byhaving a differential voltage/current change of approximately zero atthe sources of transistors 306-1/308-1 and 306-2/308-2 for a non-zerodifferential voltage/current change at the first and second differentialoutputs 314-1 and 314-2 as discussed above).

FIG. 4 illustrates a differential amplifier 400 according to an aspectof the present invention. The differential amplifier 400 again providesa cascoded arrangement of transistors that provides significant gainenhancement over the cascoded arrangement of the conventionaldifferential amplifier 100 of FIG. 1.

The differential amplifier 400 can include differential transistor pair402-1 and 402-2 and cascode transistor pairs 406-1/408-1 and406-2/408-2. Transistor 402-1 can be coupled to a first component of adifferential input 410-1. Transistor 402-2 can be coupled to a secondcomponent of a differential input 410-2. The differential transistorpair 402-1 and 402-2 can be coupled to a bias current source 412.

As further shown in FIG. 4, the transistor 402-1 can be coupled tocascode transistors 406-1 and 408-1. Specifically, the drain oftransistor 402-1 can be coupled to the sources of cascode transistors406-1 and 408-1. Similarly, the transistor 402-2 can be coupled tocascode transistors 406-2 and 408-2. Specifically, the drain oftransistor 402-2 can be coupled to the sources of transistors 406-2 and408-2. Further, the drains of the transistors 406-1 and 408-1 can becoupled to a first component of a differential output 414-1. Likewise,the drains of the transistors 406-2 and 408-2 can be coupled to a secondcomponent of the differential output 414-2.

The differential amplifier 400 capacitively couples the firstdifferential output 414-1 to the transistor 408-2 and capacitivelycouples the second differential output 414-2 to the transistor 408-1.Specifically, the gate of the transistor 408-1 can be coupled to thesecond differential output 414-2 through a capacitor 418-1. The gate ofthe transistor 408-2 can be coupled to the first differential output414-1 through a capacitor 418-2. Further, the transistors 406-1 and406-2 are no longer configured as diode followers. Instead, the gate ofthe transistor 406-1 can be coupled through a switch 416-1 to the gateof the transistor 408-1 and the gate of the transistor 406-2 can becoupled through a switch 416-2 to the gate of the transistor 408-2. Thegates of the transistors 406-1 and 406-2 can also be coupled to biasing(labeled as “BIAS” in FIG. 4 for simplicity). For continuous timeoperation, resistors, for example, can be used in lieu of the switches416-1 and 416-2 having values that can be dependent on a requiredfrequency of operation of the amplifier 200.

The configuration of the differential amplifier 400 ensures the voltageapplied to the gates of the transistors 406-1 and 406-2 can be a fixedreference voltage (by way of coupling to the biasing voltage). Further,the configuration of the differential amplifier 400 can force the samevoltage to be applied to the gates of the transistors 406-1 and 408-1along with forcing the same voltage to be applied to the gates of thetransistors 406-2 and 408-2. In the differential amplifier 400, thetransistors 406-1 and 406-2 are no longer configured as voltagefollowers tied to differential outputs 414-1 and 414-2, respectively.

As with the differential amplifiers 200 and 300 of the presentinvention, the differential amplifier 400 can be configured to provide aideal voltage change of approximately zero at the sources of transistors406-1 and 408-1 (and, correspondingly, at the sources of the transistors406-2 and 408-2) for a change in voltage at the drains of thetransistors 406-1 and 408-1 (and, correspondingly, at the drains of thetransistors 406-2 and 408-2). In doing so, the differential amplifier400 can provide significant gain enhancement over the cascadedarrangement of the conventional differential amplifier 100 of FIG. 1.

The benefits of the differential amplifier 400 and the ability of thedifferential amplifier 400 to provide significant gain enhancement canbe shown by way of example operation of the differential amplifier 400.Specifically, the differential amplifier 400 can begin in a reset mode.In reset mode, the first and second differential inputs 410-1 and 410-2can be shorted. Additionally, the switches 416-1 and 416-2 can beclosed. With the switch 416-1 closed, the voltage applied to the gatesof the transistors 406-1 and 408-1 can be forced to be the same (e.g.,forced to a reference voltage level supplied by the biasing voltageBIAS). Further, with the switch 416-2 closed, the voltage applied to thegates of the transistors 406-2 and 408-2 can be forced to be the same(e.g., forced to a reference voltage level supplied by the biasingvoltage BIAS).

After reset, the switches 416-1 and 416-2 can be opened. Further,differential input signals can be applied to the differential inputs410-1 and 410-2. When there is a change in the voltage provided by thedifferential outputs 414-1 and 414-2, the sources of the transistors406-1 and 406-2 can correspondingly change but only by an amount that isproportional to their intrinsic gain. Specifically, for a +1 V change atthe differential output 414-1, the change in voltage at the source ofthe transistor 406-1 can be proportional to the intrinsic gain of thetransistor 406-1 and can be based on the reference voltage supply BIAS.

Likewise, for a corresponding −1 V change at the differential output414-2, the change in voltage at the source of the transistor 406-2 canbe proportional to the intrinsic gain of the transistor 406-2 and can bebased on the reference voltage supply BIAS. Accordingly, the transistors408-1 and 408-2—in order to cancel the modulation effects at the sourcesof the transistors 406-1 and 406-2 to achieve approximately zero voltagechange at the sources of the transistors 406-1 and 406-2—can be sizedlarger than the other constituent transistors but smaller relative totheir sizing in the prior described configurations and yet still achievegain enhancement (i.e., near infinite gain under ideal conditions). Thisenables the differential amplifier 400 to use smaller sized transistors,thereby reducing the amount of noise introduced during amplification.Further, by not configuring the transistors 406-1 and 406-2 as diodes,further gain enhancement can be provided.

Infinite gain conditions can approximately occur when the followingcondition is met:

R _(gm408-1) ≈R _(DS406-1) ∥R _(DS408-1) *K _(CAP)

K _(CAP) ≈C ₄₁₈₋₁/(C ₄₁₈₋₁ +C ₄₀₈₋₁)

where R_(gm408-1) is the transresistance of transistor 408-1,R_(DS406-1) is the drain-to-source resistance of transistor 406-1,R_(DS408-1) is the drain-to-source resistance of transistor 408-1,C₄₁₈₋₁ is the capacitance of capacitor 418-1, and C₄₀₈₋₁ is theeffective input capacitance of transistor 408-1.

Similar to the introduction of additional input transistors in thedifferential amplifier 300, the differential amplifier 400 can bemodified to include input transistors separately coupled to each cascadetransistor 406-1, 406-2, 408-1 and 408-2.

The differential amplifiers of the present invention can includeadditional biasing elements not shown to ensure proper operation of thetransistors (for example, to ensure operation in saturation mode) whichhave not been shown or described for simplicity. Further, thedifferential amplifiers of the present invention are not limited toimplementation using NMOS transistors but can be implemented using PMOStechnology as well as other transistor technologies including BJTs.Further, the gain enhancement structures of the present inventiondescribed above can be used for any process node with the benefitsdescribed herein becoming more advantageous with process node reduction.

FIG. 5 provides a flowchart illustrating a method 500 for providingenhanced gain according to an aspect of the present invention. Themethod 500 can enable a differential amplifier configured and operatingaccording to an aspect of the present invention to provide enhanced gainusing components (e.g., transistors) that introduce low relative noise,thereby providing high amplification while also providing high fidelityand signal quality.

At step 502, a differential input signal can be received. Thedifferential input signal can include, for example, a first component ofa differential input voltage and a second component of a differentialinput voltage. The differential input signal can be coupled to inputs ofone or more input transistors. The input transistors can form a portionof an initial or input stage of a differential amplifier. As an example,a first component of a differential input signal can be coupled to agate of one or more first input transistors and a second component ofthe differential input signal can be coupled to a gate of one or moresecond input transistors.

At step 504, a change in a differential output signal can be detected orsensed. The differential output signal can include, for example, a firstcomponent of a differential output voltage and a second component of adifferential output voltage. The differential output signal can beprovided by a cascode stage of a differential amplifier. For example, afirst component of a differential output signal can be provided by anoutput of a first cascode transistor coupled to one or more first inputtransistors in cascode. A second component of the differential outputsignal can be provided by an output of a second cascode transistorcoupled to one or more second input transistors in cascode.

The change (e.g., a voltage or current change) in the differentialoutput signal can be sensed by the first and second output or cascodetransistors. For example, a change in the first component of thedifferential output signal can be sensed by the first output transistorand a change in the second component of the differential output signalcan be sensed by the second output transistor. The first and secondoutput transistors can be configured, for example, as voltage followersor diode configured followers, to detect a change in the first andsecond components of the differential output signal, respectively. Forexample, a gate of the first output transistor can be coupled to a firstoutput of the first transistor (e.g., a drain of the first transistor)that provides the first component of the differential output signal. Asecond output of the first transistor (e.g., a source of the firsttransistor) can be coupled to an output of one or more first inputtransistors (e.g., to drains of the one or more first inputtransistors).

Similarly, a gate of the second output transistor can be coupled to afirst output of the second transistor (e.g., a drain of the secondtransistor) that provides the second component of the differentialoutput signal. A second output of the second transistor (e.g., a sourceof the second transistor) can be coupled to an output of one or moresecond input transistors (e.g., to drains of the one or more secondinput transistors).

The change in the first and second components of the differential outputsignal detected by the first and second out put transistors,respectively, can result in a change in a voltage or current level atthe second outputs of the first and second output transistors (e.g., theoutputs coupled to the input transistors). Modulation effects can beinduced at the second outputs of the first and second outputtransistors. The modulation effects can occur due to the sensed changein the differential output and due to the finite source-to-drainresistance of the constituent components of the differential amplifier.

At step 506, the change in output level (e.g., change in source voltageor current) at the second outputs of the first and second outputtransistors can be approximately matched by third and fourth outputtransistors. For example, the change in the output level of the secondoutput of the first output transistor can be matched by an approximatelyequal and opposite change in output level provided by the third outputtransistor. The change in the output level of the second output of thesecond output transistor can be matched by an approximately equal andopposite change in output level provided by the fourth outputtransistor. This step can also be considered to include approximatelycanceling the induced modulation effects of the first and second outputtransistors using the third and fourth output transistors. Themodulation effects of the first and second output transistors can becaused by the change in differential output.

The third and fourth output transistors can be cascode transistorsarranged in cascode with the first and second out transistors,respectively. The third and fourth output transistors can becross-coupled output transistors. That is, the third output transistorcan be coupled to one or more first input transistors, the firstcomponent of the differential output signal, and the second component ofthe differential output signal. For example, a gate of the third outputtransistor can be coupled to the second component of the differentialoutput signal. Likewise, the fourth output transistor can be coupled toone or more second input transistors, the second component of thedifferential output signal, and the first component of the differentialoutput signal. For example, a gate of the fourth output transistor canbe coupled to the first component of the differential output signal.

By using cross-coupled third and fourth output transistors, the changein the output levels of the second outputs of the first and secondoutput transistors can be approximately matched and furtherapproximately canceled out by the third and fourth output transistors,respectively. By approximately canceling out the change in the outputlevels of the second outputs of the first and second output transistors,the cascade transistors of the differential amplifier can provide achange in differential output with approximately no change in the outputlevels of the first and second output transistors coupled to the inputtransistors. As a result, the gain of the differential amplifier can beenhanced significantly (e.g., because a non-zero change in drain voltagecan be provided with a zero change in source voltage).

The sizes of the third and fourth output transistors can be increasedproportional to the intrinsic gains of the other transistors of thedifferential amplifier (e.g., the first and second output transistorsand the one or more first and second input transistors—which can all beof approximately the same scaling) to better approximately match andcancel out the change in the output levels of the second outputs of thefirst and second output transistors to ensure significant gainenhancement.

As a variation, the first and second output transistors canalternatively be coupled to reference voltage or current sources. Thethird and fourth transistors can be capacitively coupled to thereference sources during a first stage of operation of the differentialamplifier. During a second stage of operation, the third and fourthtransistors can be de-coupled from the reference sources and can usedstored charges from capacitors to approximately match and cancel outchanges in output levels at the second outputs of the first and secondoutput transistors.

The method 500 for providing enhanced gain according to an aspect of thepresent invention can be implemented using, for example, thedifferential amplifiers depicted in FIGS. 2-4 and described above.

While various aspects of the present invention have been describedabove, it should be understood that they have been presented by way ofexample and not limitation. It will be apparent to one skilled in thepertinent art that various changes in form and detail can be madetherein without departing from the spirit and scope of the invention.Therefore, the present invention should only be defined in accordancewith the following claims and their equivalents.

What is claimed is:
 1. An amplifier, comprising: a first transistor anda second transistor; a third transistor and a fourth transistor, asource of the third transistor coupled to a drain of the firsttransistor, a gate of the third transistor directly coupled to a drainof the third transistor, a source of the fourth transistor coupled to adrain of the second transistor, a gate of the fourth transistor directlycoupled to a drain of the fourth transistor, and a fifth transistor anda sixth transistor, a source of the fifth transistor coupled to thedrain of the first transistor, a drain of the fifth transistor coupledto the drain of the third transistor, a source of the sixth transistorcoupled to the drain of the second transistor, a drain of the sixthtransistor coupled to the drain of the fourth transistor, wherein a gateof the fifth transistor is coupled to the drains of the fourth and sixthtransistors and a gate of the sixth transistor is coupled to the drainsof third and fifth transistors.
 2. The amplifier of claim 1, wherein thegate of the fifth transistor is directly coupled to the drains of thefourth and sixth transistors and the gate of the sixth transistor isdirectly coupled to the drains of the third and fifth transistors. 3.The amplifier of claim 2, wherein: the gate and drain of the thirdoutput transistor, the drain of the fifth transistor, and the gate ofthe sixth transistor are directly coupled to a first output terminal ofthe amplifier; and the gate and drain of the fourth output transistor,the drain of the sixth transistor, and the gate of the fifth transistorare directly coupled to a second output terminal of the amplifier. 4.The amplifier of claim 1, wherein a source of the first transistor iscoupled to a source of the second transistor.
 5. The amplifier of claim4, wherein the sources of the first and second transistors are coupledto a current source.
 6. The amplifier of claim 1, wherein a gate of thefirst transistor is coupled to a first component of a differential inputof the amplifier and a gate of the second transistor is coupled to asecond component of the differential input of the amplifier
 7. Theamplifier of claim 1, wherein the fifth transistor is sized to beapproximately 20% larger than the third transistor and the sixthtransistor is sized to be approximately 20% larger than the fourthtransistor.
 8. The amplifier of claim 1, wherein the third and fifthtransistors are selected such that the following condition isapproximately met:R _(gm,X) =R _(gm,Y) ∥R _(DS,Y) ∥R _(DS,X) where R_(gm,X) is thetransresistance of the fifth transistor, R_(gm,Y) is the transresistanceof the third transistor, R_(DS,Y) is the drain-to-source resistance ofthe third transistor, and R_(DS,X) is the drain-to-source resistance ofthe fifth transistor.
 9. An amplifier, comprising: a first transistorand a second transistor; a third transistor and a fourth transistor, asource of the third transistor coupled to a drain of the firsttransistor, a gate of the third transistor coupled to a drain of thethird transistor, a source of the fourth transistor coupled to a drainof the second transistor, a gate of the fourth transistor coupled to adrain of the fourth transistor, and a fifth transistor and a sixthtransistor, a source of the fifth transistor coupled to the drain of thefirst transistor, a drain of the fifth transistor coupled to the drainof the third transistor, a source of the sixth transistor coupled to thedrain of the second transistor, a drain of the sixth transistor coupledto the drain of the fourth transistor, wherein a gate of the fifthtransistor is directly coupled to the drains of the fourth and sixthtransistors and a gate of the sixth transistor is directly coupled tothe drains of third and fifth transistors.
 10. The amplifier of claim 9,wherein the gate of the third transistor is directly coupled to thedrain of the third transistor and the gate of the fourth transistor isdirectly coupled to the drain of the fourth transistor.
 11. Theamplifier of claim 10, wherein: the gate and drain of the third outputtransistor, the drain of the fifth transistor, and the gate of the sixthtransistor are directly coupled to a first output terminal of theamplifier; and the gate and drain of the fourth output transistor, thedrain of the sixth transistor, and the gate of the fifth transistor aredirectly coupled to a second output terminal of the amplifier.
 12. Theamplifier of claim 9, wherein a source of the first transistor iscoupled to a source of the second transistor.
 13. The amplifier of claim12, wherein the sources of the first and second transistors are coupledto a current source.
 14. The amplifier of claim 9, wherein a gate of thefirst transistor is coupled to a first component of a differential inputof the amplifier and a gate of the second transistor is coupled to asecond component of the differential input of the amplifier
 15. Theamplifier of claim 9, wherein the fifth transistor is sized to beapproximately 20% larger than the third transistor and the sixthtransistor is sized to be approximately 20% larger than the fourthtransistor.
 16. The amplifier of claim 9, wherein the third and fifthtransistors are selected such that the following condition isapproximately met:R _(gm,X) =R _(gm,Y) ∥R _(DS,Y) ∥R _(DS,X) where R_(gm,X) is thetransresistance of the fifth transistor, R_(gm,Y) is the transresistanceof the third transistor, R_(DS,Y) is the drain-to-source resistance ofthe third transistor, and R_(DS,X) is the drain-to-source resistance ofthe fifth transistor.